1. Field of the Invention
The present invention is related to storage arrays, especially static random access memories (SRAMs) and more particularly to reducing SRAM power consumption.
2. Background Description
Semiconductor technology and chip manufacturing advances have resulted in a steady increase of on-chip clock frequencies, the number of transistors on a single chip and the die size itself coupled with a corresponding decrease in chip supply voltage. Generally, all other factors being constant, the power consumed by a given clocked unit increases linearly with the frequency of switching within it. Thus, not withstanding the decrease of chip supply voltage, chip power consumption has increased as well. Both at the chip and system levels, cooling and packaging costs have escalated as a natural result of this increase in chip power. For low end systems (e.g., handhelds, portable and mobile systems), where battery life is crucial, net power consumption reduction is important but, without degrading performance below acceptable levels.
To minimize power consumption, most integrated circuits (ICs) used in such low end systems (and elsewhere) are made in the well-known complementary insulated gate field effect transistor (FET) technology known as CMOS. A typical CMOS circuit includes paired complementary devices, i.e., an n-type FET (NFET) paired with a corresponding p-type FET (PFET), usually gated by the same signal. Since the pair of devices have operating characteristics that are, essentially, opposite each other, when one device (e.g., the NFET) is on and conducting (ideally modeled as a closed switch), the other device (the PFET) is off, not conducting (ideally modeled as an open switch) and, vice versa.
For example, a CMOS inverter is a series connected PFET and NFET pair that are connected between a power supply voltage (Vdd) and ground (GND). Both are gated by the same input and both drive the same output, the PFET pulling the output high and the NFET pulling the output low at opposite input signal states. Ideally, when the gate of a NFET is below some positive threshold voltage (VT) with respect to its source, the NFET is off, i.e., the switch is open. Above VT, the NFET is on conducting current, i.e., the switch is closed. Similarly, a PFET is off when its gate is above its VT, i.e., less negative, and on below VT. Thus, ideally, the CMOS inverter in particular and CMOS circuits in general pass no static (DC) current. So, ideal CMOS circuits use no static or DC power and only consume transient power from charging and discharging capacitive loads.
In practice however, transient power for circuit loads accounts for only a portion of the power consumed by CMOS circuits. A typical FET is much more complex than a switch. FET drain to source current (and so, power consumed) is dependent upon circuit conditions and device voltages. FETs are known to conduct what is known as subthreshold current below threshold for NFETs and above for PFETs. Subthreshold current increases with the magnitude of the device""s drain to source voltage (Vds) and inversely with the magnitude of the device VT. Also, there is some portion of any input transition (rise or fall), when both devices are conducting, i.e., the portion of the input transition between the turn on point of one device (e.g., above the NFET VT) and the turn off point of the other, i.e., below Vdd by more than VT for the PFET. The current flowing during this period of orthogonality when both devices are on is also known as flush current and, the power consumed is known as short circuit power. So, in addition to transient power, all CMOS circuits consume some short circuit power and some power from subthreshold currents.
For logic chips such as general and special purpose processors, non-load related power dissipation is fairly randomly distributed throughout the logic. Transient power tends to dominate logic chip power consumption. Storage arrays, however, such as random access memories (RAMs) and especially static RAMs (SRAMs), have a large areas that may remain dormant during any one operation. Thus, in these dormant areas, subthreshold leakage can become a substantial source of power consumption. Furthermore, even in portions of RAMs that are active during a typical operation, i.e., an access, and especially SRAMs, large portions of the active area are unnecessarily active.
A typical SRAM array may be organized n word lines by m bit lines (bit line pairs) by k bits. So, accessing one bit from one of the k (or more) subarrays entails selecting one of the n word lines. Of the m cells partially selected by that word line, only one (on one of the m bit lines) may actually be accessed. During a read, each of the bit line pairs rises/droops only to develop enough signal (e.g., 50 mV) for a sense amplifier. During a write, however, the pair for the cell being accessed may be driven at least what is termed xe2x80x9crail to rail,xe2x80x9d i.e., to opposite extremes (Vdd and GND). Thus, each write also consumes significant transient power.
Since low end systems may include several chips, it is important to reduce power in each. However, typically, memory accounts for a large number of those chips. Especially with low end systems those memory chips are SRAM. So, SRAM chip power is multiplied by the number of SRAM chips included. While high chip power may be tolerable for a single (e.g., processor) chip, when multiplied by a number SRAM chips it can account for a significant portion of system power, making the difference between acceptable and unacceptable system battery life.
Thus, there is a need for reduced chip power consumption and especially for chips containing arrays such as SRAMs.
It is a purpose of the invention to reduce storage array power consumption;
It is another purpose of the invention to reduce SRAM power consumption;
It is yet another purpose of the invention to reduce SRAM power consumption without impacting performance;
It is yet another purpose of the invention to reduce subthreshold leakage in SRAM arrays.
The present invention relates to a CMOS storage array such as a static random access memory (SRAM) and a sense amplifier. The SRAM may be in partially depleted (PD) silicon on insulator (SOI) and may include fully depleted (FD) FETs. A power supply select line at each row selectively increases cell supply voltage to a full supply voltage when the row is selected. A word line decoder selects a row of cells that are provided the supply voltage and cells in remaining rows are provided a reduced supply voltage. Leakage is substantially lower in said remaining rows than in said selected row. The sense amplifier may include cross coupled FD NFETs sensing stored data. A read/write-select in each bit path selectively blocks cell writes when cell contents are not being changed. Power is not expended unnecessarily writing to cells.